ALP™ — Atomic
Level Purification.
A UHV-based surface treatment — laser-heated, controlled oxidation, crystalline SiO₂ regrowth. Built for 3 nm and below.
At today's nodes, particle cleaning isn't enough. Atomic-level impurities dominate what devices do.
Traditional cleans stop at particles.
Conventional wet and cryo cleans remove particulates but leave sub-nanometre contaminants (hydrogen, carbon), disordered chemically-grown oxide, and atomic-scale interfacial defects behind. Those invisible residues drive leakage, variation and reliability loss at advanced nodes.
ALP™ operates at the atomic layer.
ALP™ removes hydrogen and carbon contaminants in UHV, reorders the disordered silicon surface, and grows a thin crystalline SiO₂ layer — verified by TEM — giving the device stack a clean, repeatable interface to build on.
UHV, laser heating, and controlled oxygen — not another wet clean.
The AtomSeal™ system combines Ultra-High Vacuum, uniform laser-based wafer heating (up to Ø300 mm), and controlled oxidation to strip atomic-level contaminants and regrow a clean, crystalline silicon-oxide interface.
- 01
Ultra-high vacuum
ALP™ runs in UHV — a regime silicon foundries traditionally haven't used. That's what makes true atom-level cleanliness reachable without re-contaminating during processing.
UHV chamber · AtomSeal™ system - 02
Uniform laser heating
Wafers up to Ø300 mm are heated uniformly with an IPG Photonics fibre-laser source — below 450 °C. Resistive heating can't match that uniformity or throughput scaling.
<450 °C · Ø300/200/150 mm - 03
Controlled oxidation
A precisely controlled oxygen flow regrows a thin crystalline SiO₂ layer on the ordered silicon surface — sealing and protecting it for downstream processing.
Thin crystalline SiO₂ (~1 nm, TEM-verified) - 04
Clean surface, ready for the stack
Hydrogen and carbon contaminants are gone, the surface is ordered, and the interface behaves the way your device design assumes it will.
Front- or back-end-of-line · FEOL/BEOL
Three proposals. One shared flow. No mystery.
SisuSemi publishes three standard ways to start: treat your components, study your surface, or run a full wafer-level feasibility. Each one follows the same six-step engagement.
Treat existing components to compare performance before and after. Fastest way to see if ALP™ unlocks value on your device.
- KPI
- Leakage current
- Sample
- 12 chips
- What you get
- 10–40% of potential unlocked
Analyse wafer surface quality and composition. Improve surface at the atomic level and compare against matched references.
- KPI
- Defects, contaminants, surface structure
- Sample
- 2–3 reference + 2–3 treated wafers
- What you get
- Full surface/interface report
Integrate ALP™ as part of a critical process step. Demonstrate yield and performance improvement on your own flow.
- KPI
- Component performance · chip-to-chip variation · yield
- Sample
- From 5 wafers (+ controls), or 1 per recipe
- What you get
- Production-representative proof
- 01Project Planscope, timeline, cost, objectives, KPIs.
- 02Pre-measurementssample characterisation before treatment.
- 03ALP™ treatmentclean and passivate in the AtomSeal™ UHV system.
- 04Post-measurementsrepeat the same characterisation on treated samples.
- 05Analysis & insightsidentify impurities and improvement potential.
- 06Samples back to youcontinue the process at your facility.
The questions fab engineers usually ask first.
What exactly is ALP™?
ALP™ (Atomic Level Purification) is a surface treatment that uses Ultra-High Vacuum, elevated temperature (below 450 °C) and controlled oxidation to clean the silicon surface, restore the crystalline structure of surface atoms, and regrow a thin crystalline SiO₂ protective layer (~1 nm, verified by TEM).
How is ALP™ different from SC-1 / SC-2 / cryo cleans?
Traditional cleans target particulate contamination above tens of nanometres. ALP™ operates at the atomic layer — inside a UHV chamber — and addresses sub-nanometre residues and interfacial disorder that bulk chemistries can't resolve. Silicon manufacturing has traditionally not used UHV.
Do I need to buy a new tool?
The AtomSeal™ system is the production-grade ALP™ platform, built with IPG Photonics laser heating. It supports Ø300 mm, Ø200 mm and Ø150 mm wafers. Most customers start with a feasibility engagement — samples run in our Turku lab — and only commit to a system once the numbers line up.
What nodes and devices does ALP™ apply to?
ALP™ targets 3 nm and below in logic, where atomic-scale cleanliness becomes a hard limit. Case studies span memory/logic MOSCaps, photodetectors, p-n diodes for satellites and nuclear applications, solar cells, and post-dicing sensor sidewalls.
How do I start an engagement?
Three published options: Components (12 chips, KPI = leakage), Surface quality (2–3 reference + 2–3 treated wafers, KPIs = defects/contaminants/structure), or Feasibility (5+ wafers, KPIs = performance, variation, yield). Each one follows the same flow: Project Plan → Pre-measurements → Treatment → Post-measurements → Analysis → Samples back.
How do you protect customer IP?
Engagements run under mutual NDA. All process data, metrology and tailored recipes are customer-confidential. Our own IP is protected by a global patent portfolio, with grants in Japan, Taiwan and via the European Patent Office.
Send samples.
See the numbers on your stack.
Pick one of the three published engagements — Components (12 chips), Surface quality (wafers), or Feasibility (wafers on your flow) — and we'll quote scope, timeline and KPIs.